Substituting for V C in the equation I B=(V C-V BE)/R B, The decrease in I B produces less I C which, in turn, drops less voltage across R C and thus offsets the decrease in V C.Īnalysis of a Collector-Feedback Bias CircuitĪssuming that I C > I B, V C ≈ V CC - I C R C. When V C decreases, there is a decrease in voltage across R B, which decreases I B. If I C tries to increase, it drops more voltage across R C, thereby causing V C to decrease. The negative feedback creates an “offsetting” effect that keeps the Q-point stable. V C provides the bias for the base-emitter junction. 11, R B is connected to the collector rather than to V CC, as it was in the base bias arrangement. Voltages with respect to ground are indicated by a single subscript.8(a), which has been redrawn in part (b) for analysis, gives: Kirchhoff’s voltage law applied around the base-emitter circuit in Fig.
Kirchhoff’s voltage law can be applied to develop a more accurate formula for I E for detailed analysis. The approximation that V E ≈ -1 V is useful for troubleshooting to circumvent detailed calculations.
V E is one diode drop less than this.įigure 8: An NPN transistor with emitter bias. 8, the small I B causes V B to be slightly below ground. It uses both a positive and a negative supply voltage.
Voltage-divider bias is widely used because reasonably good bias stability is achieved with a single supply voltage.Įmitter bias provides excellent bias stability in spite of changes in or temperature. If R TH/β DC is small compared to R E, the result is the same as for an unloaded voltage divider. Applying Kirchhoff’s voltage law around the equivalent base-emitter loop gives The Thevenin equivalent of the bias circuit, connected to the transistor base, is shown in the box in Fig. The voltage at point A with respect to ground is 7(b).Īpply Thevenin’s theorem to the circuit left of point A, with V CC replaced by a short to ground and the transistor disconnected from the circuit. 7(a), looking out from the base terminal, the bias circuit can be redrawn as shown in Fig. To analyze a voltage-divider biased transistor circuit for base current loading effects, we will apply Thevenin’s theorem.įor the circuit in Fig. Thevenin’s Theorem Applied to Voltage-Divider Bias V CEQ, I CQ, and I BQ are DC Q-point values with no input sinusoidal voltage applied. Point B corresponds to the negative peak, and point Q corresponds to the zero value of the sine wave. 5 corresponds to the positive peak of the sinusoidal input voltage. This causes I C to vary 10 mA above and below its Q-point value of 30 mA.Īs a result of the variation I C, V CE varies 2.2 V above and below its Q-point value of 3.4 V. AC quantities are indicated by lowercase italic subscripts.įigure 5: Variations in collector current and collector-to-emitter voltage as a result of a variation in base current.Ī sinusoidal voltage, V in, is superimposed on V BB, causing I B to vary sinusoidally above and below its Q-point value of 300 A. In this region, the output voltage is ideally a linear reproduction of the input.įigure 5 shows an example of the linear operation of a transistor. The region along the load line including all points between saturation and cutoff is the linear region of the transistor’s operation.
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